An AI hardware engineer · designed to typ, checked to max

AI that engineers a circuit, not AI that draws one.

Describe the board. Typmax picks real parts, wires them by rule, checks every number against the datasheet, and hands you a KiCad project with the proof attached.

The parts you name decide which records we verify first. No spam; one email when your seat opens.

you ›
i2c.pullup_window · I2C0 · 400 kHzPASS
computedRmin 0.000 kΩ · Rmax 0.00 kΩ · Cb 105 pF
chosenR1, R2 = 4.7 kΩ
sourceTI SLVA689 · NXP UM10204
net.level_compat · SDA · 2 receiversFAIL
computednet high can reach 0.00 V · AHT20 tolerates ≤ 3.60 V at rail min
assumesVDD33 spans 3.0–3.6 V (declared)
fixset_rail_range VDD33 3.3 V ±3 % · or level-shift SDA/SCL
power.rail_capability · VDD33 · AMS1117-3.3PASS
computedload 0 mA vs i_out_max 1000 mA · margin 20 % as policy
unverifiedublox/max-m10s i_peak llm_extracted
risk.lipo_charging · TP4056 · 500 mAHUMAN REVIEW
ranprog resistor · thermal at VIN max · connector polarity
thenstops here. A person signs off on battery charging.
4 checks · 1 fail · 1 needs a humangps-tracker.kicad_pro · ERC clean
What we're building

A design you can trust because it shows its work.

Ask a language model for a schematic and you get a drawing that looks right. On the public benchmarks about 8 % of those drawings are fully correct, and each edit makes them worse — from 80 % to 26 % over fifteen changes. The model recalls a rule of thumb, drops a pull-up, forgets which pin is a boot strap, and there is nothing in the loop that would notice.

Typmax turns that around. The model is the planner: it proposes small, typed changes to a structured design. Deterministic code does the engineering: it wires by rule, derives every net, sizes every pull-up, checks every logic level and every rail against the parts' own datasheets, and writes the KiCad files. The model never touches them and never holds the design in its head.

The goal is the whole board. Today that means the schematic: real parts, every net derived, every check computed and cited. Next it means layout — the same engine carrying the same constraints onto the PCB, with the layout tool's own design-rule check in the loop, so a rule that held on the schematic still holds on copper. At every stage the principle is the same: every result arrives with its arithmetic, its assumptions, the app note it came from, and an honest list of what was not verified.

And when a domain is dangerous — battery charging, mains, motor drive — it runs its checks and then insists on a human.

You

Describe it

"ESP32-S3, BME280 on I²C at 400 kHz, GPS on UART, 3.3 V from an LDO."

Language model

Plans small edits

Add this part, bind that pin, set this bus speed. Typed, checked, revertible.

never writes files · never holds state
Engine

Engineers it

Rules from the datasheets, real part records, derived nets, every number computed and cited.

You, again

Open it in KiCad

A project with real parts, plus the dossier that says why each check passed — or didn't.

What you get

Real parts, real rules, your files.

Every finding shows its work

Computed values, the assumptions used, the inputs that weren't verified, and the app note the formula came from. A pass without evidence doesn't exist.

i2c.pullup_window · 0.967–8.43 kΩ · TI SLVA689 §3

Parts that are real

Every part is a record with pins, levels, currents and limits taken from its datasheet, and each value is tagged by who verified it. You see when a number came from a model instead of a person.

provenance: datasheet · vendor_db · llm_extracted · human

Nothing gets redrawn

Edits are small and typed, with a revision check. What you fixed stays fixed; the model can't regenerate your design by accident.

30 typed ops · expected_rev · full re-validation per batch

KiCad-native, never gated

Schematic, project, netlist and BOM in KiCad's own formats. Export is always on. No format sits between you and your board.

.kicad_sch · .kicad_pro · netlist · BOM · ERC clean

Rules are data, with sources

Constants live per part and per mode, citing the app note. Add a rule and every design ever made is re-checked against it.

MCP73831 1000 V·kΩ/mA vs TP4056 1100–1200 · I²C Fm+ 550 pF

Stops for the dangerous parts

LiPo charging, mains, motor drive: it runs every deterministic check it has, then marks the design for human review. That never gets softened.

risk_class: human_review_required
Limits

What it will not do, yet.

We'd rather tell you now than have you find out on a board.

Where it is

Schematic today. Workspace next. Then the board.

Now

Engine, compiler, agent loop

  • Rules for I²C, UART, SPI, power, boot straps, logic levels
  • KiCad project output, ERC-checked
  • Six boards designed from an empty file, judged by the engine, 6 of 6
Next

Private alpha

  • A schematic an engineer can review at a glance
  • Browser workspace: chat · schematic · dossier
  • Back-powering and rail-sequencing checks
Then

Public beta

  • Bring your own part record
  • Human-verified catalog around ESP32-class boards, in waitlist order
  • Layout rules written into the KiCad project
Later

The board itself

  • PCB layout with KiCad's design-rule check in the loop
  • Schematic rules re-run on measured trace lengths, not assumptions
  • SPICE for the corners rules can't close
Waitlist

Tell us what you're building.

Seats open in small batches as the catalog grows. The parts you name go to the front of the verification queue.